In recent years, electronic instruments are becoming smaller, thinner, and higher in performance by developments of technologies for semiconductor integrated circuits. In accordance with this, a semiconductor chip and an electronic component are also becoming smaller. Under these circumstances, in order to house, in a small case, a circuit having a larger scale and being more complex, a semiconductor package and the electronic component are required to be mounted with higher density than before. To meet these requirements, the electronic component having a passive element (such as a resistor, capacitor, or the like) mounted on a printed-wiring board along with the semiconductor package is mounted, by a surface-mount technology, as a chip component of a ceramics package. The size of the electronic component is becoming smaller from 1005 size to 0603 size.
However, even though the semiconductor integrated circuit and the passive element are becoming smaller, it is always necessary to have a two-dimensional space for mounting components thereon so as to connect the semiconductor integrated circuit and the passive component. This hinders attaining further miniaturization of entire apparatus and a further shorter electrical distance between the semiconductor integrated circuit and the passive component.
To solve the above problems, a structure in which the electronic component is mounted on the semiconductor chip is proposed. Such a structure is disclosed in Japanese Laid-Open Publication No. 246535/2002 (published on Aug. 30, 2002). In the structure, a surface of a semiconductor chip on which a plurality of connection electrodes are arranged is so covered with a lower insulating film that the connection electrodes are left uncovered with the lower insulating film. On the lower insulating film, a plurality of wiring patterns are formed. One end of the wiring patterns is connected with the connection electrodes and the other end has component connection part. The wiring patterns are so covered with an upper insulating film that the component connection parts are left uncovered with the upper insulating film, and a discrete electronic component is connected between different component connection parts.
However, conventional semiconductor integrated circuits have following problems. FIG. 10 illustrates a conventional semiconductor integrated circuit 81 concretely disclosed in the above Japanese Laid-Open Publication.
In the semiconductor integrated circuit 81, a plurality of electrode pads 83 are provided in edge portions of the surface of a semiconductor chip 82. The surface of the semiconductor chip 82 is covered with a lower insulating film 84, except for portions where the electrode pads 83 are provided. A plurality of wires 85 are formed on the lower insulating film 84. One end of each of the wires 85 is connected to the electrode pad 83, and the other end has a connection pad. A component connection terminal 87 made of solder is formed on the connection pad. The wires 85 are covered with an upper insulating film 86, except for portions where the component connection terminals 87 are formed on the connection pads. A discrete electronic component 88 is connected between component connection terminals 87 of different wires 85.
In the semiconductor integrated circuit 81, an electronic component 88 is mounted on the surface of the semiconductor chip 82. The problem here is that the number of the electronic components 88 mounted is limited by an area of the semiconductor chip 82. Moreover, in case of CSP (Chip Size Package) which is the same in size as the semiconductor chip 82, an external connection terminal 89 is provided on the surface of the semiconductor chip 82. The problem here is that the electronic component 88 mounted is limited by an area of the semiconductor chip 82 and a height of the external connection terminal 89.